1. Field of the Invention
The present invention relates to a switched capacitor circuit, a switched capacitor filter, and a sigma-delta A/D converter.
2. Description of the Related Art
A passive type switched capacitor filter that uses a switched capacitor circuit can serve as a discrete-time analog filter with low electric power consumption. It has also been reported that a sigma-delta type A/D converter in which the passive type switched capacitor filter is used as a loop filter operates at high speed even as its electric power consumption remains low (refer to Feng Chen, Bosco Leung, “A 0.25 mW 13b Passive ΣΔ Modulator for a 10 MHz IF Input,” in IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, February 1996, pp. 58-59, and to Feng Chen, Srinath Ramaswamy, Bertan Bakkaloglu, “A 1.5V 1 mA 80 dB Passive ΣΔ ADC in 0.13 μm Digital CMOS Process,” in IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, February 2003, pp. 54-55).
FIG. 15 is an explanatory figure for explaining a loop filter circuit 10a that, with regard to its filter function only, is equivalent to the loop filter in the sigma-delta A/D converter that uses the known passive type switched capacitor filter, described in Feng Chen, Bosco Leung, “A 0.25 mW 13b Passive ΣΔ Modulator for a 10 MHz IF Input,” in IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, February 1996, pp. 58-59. FIG. 16 is an explanatory figure that shows that shows waveforms of clock signals that are input to the loop filter that is shown in FIG. 15. The symbols φ1 and φ2 adjacent to various switches in the loop filter circuit 10a shown in FIG. 15 indicate that those switches become on when the clock signals φ1 and φ2 shown in FIG. 16 respectively become high.
As shown in FIG. 15, the known loop filter circuit 10a is configured from capacitors C1, C2, C3, CR1, CR2, CR3 and from switches that control the accumulation of charges in and the discharge of charges from the capacitors. The portions of the loop filter circuit 10a shown in FIG. 15 that are enclosed by the broken lines labeled 11a, 11b, 11c perform operations that move charges through the capacitors CR1, CR2, CR3 in two directions. For example, focusing on the portion enclosed by the broken line 11a, when the clock signal φ2 becomes high, an electric current flows to the capacitor CR1 from an input terminal IN and a charge is accumulated in the capacitor CR1. Then, when the clock signal φ1 becomes high, the charge that has been accumulated in the capacitor CR1 is discharged. The accumulation and the discharge of the charge are thus performed according to the states of the clock signals φ1 and φ2. It can therefore be seen that the loop filter circuit 10a shown in FIG. 15 is the same sort of filter as a continuous-time RC filter circuit 10b that is shown in FIG. 17.
As shown in Feng Chen, Bosco Leung, “A 0.25 mW 13b Passive ΣΔ Modulator for a 10 MHz IF Input,” in IEEE Int. Solid State Circuits Conf. Dig. Tech. Papers, February 1996, pp. 58-59, the sampling frequency for the loop filter circuit 10a in FIG. 15 is 10 MHz, the filter's poles are at 8 kHz and 34 kHz, and the zero point is at 750 kHz. Based on these conditions, the capacitances of the various capacitors in the loop filter circuit 10a in FIG. 15 are calculated as 0.2 pF for CR1, 23 pF for C1, 2.5 pF for CR2, 0.5 pF for C2, 2.5 pF for CR3, and 4.15 pF for C3. For the input and output voltages under these conditions, the frequency characteristics are shown in FIG. 18, and the arrangement of the poles and the zero points is shown in FIG. 19. In the graph of the frequency characteristics of the loop filter circuit 10a shown in FIG. 18, the horizontal axis is the frequency, and the vertical axis is the gain. In FIG. 19, the horizontal axis is the real number axis (Re), the vertical axis is the imaginary number axis (Im), the position of each pole is indicated by x, and the position of each zero point is indicated by ◯.